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ISL12022MR5421
7
FN7576.3
June 7, 2012
OSCILLATOR ACCURACY
ΔFoutI
Oscillator Initial Accuracy
VDD = 3.3V
-2
+8
ppm
5, 16
ΔFoutR
Oscillator Accuracy after Reflow Cycle
VDD = 3.3V
±5
ppm
5, 16
ΔFoutT
Oscillator Stability vs Temperature
VDD = 3.3V
±2
ppm
5, 17
ΔFoutV
Oscillator Stability vs Voltage
2.7V
≤ VDD ≤ 5.5V
-3
+3
ppm
18
Temp
Temperature Sensor Accuracy
VDD = VBAT = 3.3V
±2
°C
12
IRQ/FOUT (OPEN DRAIN OUTPUT)
VOL
Output Low Voltage
VDD = 5V, IOL = 3mA
0.4
V
VDD = 2.7V, IOL = 1mA
0.4
V
DC Operating Characteristics RTC Test Conditions: VDD = +2.7 to +5.5V, TA = -40°C to +85°C, unless otherwise stated. Boldface
limits apply over the operating temperature range, -40°C to +85°C. (Continued)
SYMBOL
PARAMETER
CONDITIONS
MIN
(Note 6)
TYP
(Note 7)
MAX
(Note 6)
UNITS
NOTES
Power-Down Timing Test Conditions: VDD = +2.7 to +5.5V, Temperature = -40°C to +85°C, unless otherwise stated. Boldface limits apply
over the operating temperature range, -40°C to +85°C.
SYMBOL
PARAMETER
CONDITIONS
MIN
(Note 6)
TYP
(Note 7)
MAX
(Note 6)
UNITS
NOTES
VDDSR-
VDD Negative Slew Rate
10
V/ms
11
VDDSR+
VDD Positive Slew Rate, Minimum
0.05
V/ms
15
I2C Interface Specifications Test Conditions: VDD = +2.7 to +5.5V, Temperature = -40°C to +85°C, unless otherwise specified.
Boldface limits apply over the operating temperature range, -40°C to +85°C.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 6)
TYP
(Note 7)
MAX
(Note 6)
UNITS
NOTES
VIL
SDA and SCL Input Buffer LOW
Voltage
-0.3
0.3 x VDD
V
VIH
SDA and SCL Input Buffer HIGH
Voltage
0.7 x VDD
VDD + 0.3
V
Hysteresis
SDA and SCL Input Buffer
Hysteresis
0.05 x VDD
V12, 13
VOL
SDA Output Buffer LOW Voltage,
Sinking 3mA
VDD = 5V, IOL = 3mA
0
0.02
0.4
V
CPIN
SDA and SCL Pin Capacitance
TA = +25°C, f = 1MHz,
VDD = 5V, VIN =0V, VOUT = 0V
10
pF
12, 13
fSCL
SCL Frequency
400
kHz
tIN
Pulse Width Suppression Time at
SDA and SCL Inputs
Any pulse narrower than the
max spec is suppressed.
50
ns
tAA
SCL Falling Edge to SDA Output
Data Valid
SCL falling edge crossing 30%
of VDD, until SDA exits the 30%
to 70% of VDD window.
900
ns
tBUF
Time the Bus Must be Free Before
the Start of a New Transmission
SDA crossing 70% of VDD
during a STOP condition, to
SDA crossing 70% of VDD
during the following START
condition.
1300
ns
tLOW
Clock LOW Time
Measured at the 30% of VDD
crossing.
1300
ns
tHIGH
Clock HIGH Time
Measured at the 70% of VDD
crossing.
600
ns
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